1. Field of the Invention
The present invention relates to a microcomputer, and particularly to an improvement in processing speed.
2. Description of the Prior Art
FIG. 3 is a diagram showing a microcomputer M as an prior art. In the Figure, numeral 1 represents a ROM storing micro instructions (hereinafter called a micro ROM), numeral 2 represents an address field in the micro ROM, numeral 3 represents a micro instruction field, numeral 4 represents an address decoder for the micro ROM 1, numeral 5 denotes an execution unit, numeral 6 denotes an instruction prefetch buffer for fetching various instructions, numeral 7 denotes a bus interface unit, and numeral 8 denotes a data pointer for showing data to be read out next in the instruction prefetch buffer. Numeral 9 denotes an external data bus, numeral 10 denotes an external address bus, and numeral 11 denotes an external control signal line. The microcomputer M is connected to an external memory and peripherals through the buses 9, 10, and the signal line 11.
The operation will be explained hereinafter. FIG. 4 shows the operation of the microcomputer in the prior art.
Here, it is assumed that the microcomputer executes instructions which use immediate data. A RAM of an external memory 19 stores user programs ADD R.sub.A, IMML, etc. Those programs are transferred to the prefetch buffer 6 in such a way as ADD R.sub.A, IMML, IMMH, SUB R.sub.B through the bus lines 9, 10, and 11 at every step instruction.
Referring to FIG. 4, in a cycle which begins from a time t0, the execution unit 5 requests the bus interface unit 7 for next instruction code in accordance with the last micro instruction of the previous instruction, and "1" is added to contents of a program counter 18. The bus interface unit 7 receives this request and add "1" to the data pointer 8, and the data (instruction code) from the instruction prefetch buffer 6 is sent to the address decoder 4 if the data is effective. This data is decoded by the address decoder 4, the micro ROM 1 is accessed, the micro ROM 1 constructs an instruction code, and a micro instruction which is to be executed firstly is outputted from the micro ROM 1 to the execution unit 5. At the same time, the micro ROM 1 outputs an address of the micro instruction, which is to be accessed next, to the address decoder 4.
In a cycle which begins at a time t1, the execution unit 5 executes firstly the inputted micro instruction. Then, the execution unit 5 requests the bus interface unit 7 for the immediate data which is necessary to execute the instruction, and adds the number of words of the immediate data, which are previously read out, to the contents of program counter 18. The bus interface unit 7 reads out the next data (immediate data) responding to a request from the instruction prefetch buffer 6 if the data is effective, and add the number of words of the data to the data pointer 8.
At a next t2 cycle, the execution unit 5 requests the bus interface unit 7 for the next instruction code in accordance with the previous micro instruction. The micro ROM 1 is again accessed in accordance with the instruction code (data) outputted from the instruction prefetch buffer 6. Hereinafter, the above-mentioned operations at t0 and t1 are repeated, so that the microcomputer M executes each instruction of the user programs.
Since the conventional microcomputer executes the instructions in such a way as described above, unless after the executions of each micro instruction in which the last data in the instruction is requested, the position of the next instruction code in the instruction prefetch buffer 6 is unknown.